INTERNSHIP FOR VLSI DESIGN ENGINEERS 2014/15 BATCH IN INDIA

Experience in UVM System Verilog based verification High-energy individual with strong commitment, good team player, and comfortable in a fast-paced environment. The person will be part of the VLSI design team, doing verification for DSL chips of Ikanos He / She will be responsible for defining testbench architecture of blocks and creating testplans. He / She will be responsible for verifying the block, creating direct and constrained random testcases. He / She will be responsible for functional and code coverage of his blocks.